Event language
UI language
The rise of open-RTL cores such as RISC-V promises greater transparency than ever into the internal functioning of a CPU. But how exactly can one take advantage of this?<br><br>In this talk, I demonstrate the utility of an open-RTL RISC-V by debugging our Rust-based OS, Xous, using a system-level simulation called Verilator. With this technique, we can access internal state that would normally be very difficult to see through software-only means, such as transitions between kernel and usemode, page table faults and cache misses. The technique could also have great utility in assessing mitigations to Spectre-like sidechannels.
